Test Cost Analysis for 3D Die-to-Wafer Stacking

  title={Test Cost Analysis for 3D Die-to-Wafer Stacking},
  author={Mottaqiallah Taouil and Said Hamdioui and Kees Beenakker and Erik Jan Marinissen},
  journal={2010 19th IEEE Asian Test Symposium},
The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), a technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D2W) stacking seems the most favorable approach, due to the ability of Known Good Die stacking. Minimizing the test cost for such a stacking approach is a challenging task. Every manufactured chip… CONTINUE READING
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