Test Challenges in Nanometer Technologies

@article{Kundu2001TestCI,
  title={Test Challenges in Nanometer Technologies},
  author={Sandip Kundu and Sujit T. Zachariah and Sanjay Sengupta and Rajesh Galivanche},
  journal={J. Electronic Testing},
  year={2001},
  volume={17},
  pages={209-218}
}
Scaling transistor feature size allows greater density, higher performance and lower cost. The unrelenting pursuit of device scaling has enabled MOS gate dimensions to be reduced from 10μm in the 1970's to a present day size of 0.1μm. Conventional scaling of gate oxide thickness, source/drain extension, junction depths, and gate lengths have brought about several new technology issues invalidating some earlier methods for testing ICs. To enable testing devices into the 21 century, new… CONTINUE READING
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MOS Scaling: Transistor Challenges in the 21 Century

  • Scott Thompson, Paul Packan, Mark Bohr
  • Intel Technology Journal,
  • 1998
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MOS Scaling : Transistor Challenges in the 21 st Century ”

  • Scott Thompson, Paul Packan, Mark Bohr

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