Test Bus Sizing for System-on-a-Chip

@article{Iyengar2002TestBS,
  title={Test Bus Sizing for System-on-a-Chip},
  author={Vikram Iyengar and Krishnendu Chakrabarty},
  journal={IEEE Trans. Computers},
  year={2002},
  volume={51},
  pages={449-459}
}
ÐSystem-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model… CONTINUE READING