Waicukauski, "On Computing the Sizes of Detected Delay Faults,
- V. S. Iyengar, B. K. Rosen, J.A
- IEEE Trunsactions oii Coniputer-Aidcd Design of…
The increasing emphasis on AC testing of integrated circuits is driven by the combination of tighter quality requirements and sensitivity of high performance circuits to delay defects. The areas of fault modeling, fault simulation and test generation as applied to AC testing have received most of the attention so far. The relatively unexplored side of AC test is the determination of the test application timing. Tight timings during test application are crucial to the success of the AC test. This paper formulates the problem of generating tight test application timings and presents some sample results using a heuristic algorithm.