Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip

@article{Iyengar2003TestAM,
  title={Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip},
  author={Vikram Iyengar and Krishnendu Chakrabarty and Erik Jan Marinissen},
  journal={IEEE Trans. Computers},
  year={2003},
  volume={52},
  pages={1619-1632}
}
We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm for test scheduling. Test scheduling is tightly integrated with TAM optimization and it incorporates… CONTINUE READING
Highly Cited
This paper has 142 citations. REVIEW CITATIONS

18 Figures & Tables

Topics

Statistics

01020'02'04'06'08'10'12'14'16'18
Citations per Year

142 Citations

Semantic Scholar estimates that this publication has 142 citations based on the available data.

See our FAQ for additional information.