Template-driven parasitic-aware optimization of analog integrated circuit layouts

Abstract

Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated circuits. In order to ensure desired circuit performance, bounds on layout parasitics' magnitudes are determined first. Then, graph techniques are coupled with mathematical… (More)
DOI: 10.1145/1065579.1065748

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@article{Bhattacharya2005TemplatedrivenPO, title={Template-driven parasitic-aware optimization of analog integrated circuit layouts}, author={Sambuddha Bhattacharya and Nuttorn Jangkrajarng and C.-J. Richard Shi}, journal={Proceedings. 42nd Design Automation Conference, 2005.}, year={2005}, pages={644-647} }