Temperature constrained power management scheme for 3D MPSoC

@article{Aggarwal2012TemperatureCP,
  title={Temperature constrained power management scheme for 3D MPSoC},
  author={Anupama Aggarwal and Sumeet S. Kumar and Amir Zjajo and Rene van Leuken},
  journal={2012 IEEE 16th Workshop on Signal and Power Integrity (SPI)},
  year={2012},
  pages={7-10}
}
This paper proposes a new temperature constrained power management scheme for 3D MPSoCs that utilizes instantaneous temperature monitoring along with information on the physical structure of the stack to determine operating V-F levels for processing elements (PE). The scheme implements a weighted policy that prevents PEs deep inside the stack from being turned off, maintains operating temperatures stable and within safe margins, and reduces overall execution time by up to 19.55%.