Temperature-aware test scheduling for multiprocessor systems-on-chip

@article{Bild2008TemperatureawareTS,
  title={Temperature-aware test scheduling for multiprocessor systems-on-chip},
  author={David R. Bild and Sanchit Misra and Thidapat Chantem and Prabhat Kumar and Robert P. Dick and Xiaobo Sharon Hu and Li Shang and Alok N. Choudhary},
  journal={2008 IEEE/ACM International Conference on Computer-Aided Design},
  year={2008},
  pages={59-66}
}
Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integrated circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. We first study the power impact of scan chain testing for the ISCAS89 benchmarks. We find that the scan-chain test power consumption is 1.6x higher for at-speed testing than… CONTINUE READING
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