Temperature-aware task scheduling heuristics on Network-on-Chips


Chip temperature becomes a critical design issue with technology scaling to nanometer-scale, especially for NoC systems with large number of cores and shrunken core size. To reduce peak temperature and balance spatial temperature distribution on NoC-based multi-cores chips, this paper proposes a temperature-aware task scheduling approach. The thermal… (More)
DOI: 10.1109/ISCAS.2016.7539126


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@article{Cao2016TemperatureawareTS, title={Temperature-aware task scheduling heuristics on Network-on-Chips}, author={Shan Cao and Zoran A. Salcic and Yingtao Ding and Zhaolin Li and Shaojun Wei and Xianli Zhao}, journal={2016 IEEE International Symposium on Circuits and Systems (ISCAS)}, year={2016}, pages={2603-2606} }