Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

@article{Coskun2009TemperatureAC,
  title={Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures},
  author={Ayse K. Coskun and Andrew B. Kahng and Tajana Simunic},
  journal={2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools},
  year={2009},
  pages={183-190}
}
D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates temperature- induced problems that affect system reliability, performance, leakage power and cooling cost. In addition, the overhead due to through-silicon-vias (TSVs) and scribe lines contribute to the overall area, affecting wafer utilization and yield. As any of the aforementioned parameters can limit the 3D stacking process… CONTINUE READING

Citations

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Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs

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Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits

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Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors

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Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs

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