Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology

@article{Kumar2006TemperatureVI,
  title={Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology},
  author={Ranjith Kumar and Volkan Kursun},
  journal={2006 49th IEEE International Midwest Symposium on Circuits and Systems},
  year={2006},
  volume={2},
  pages={226-230}
}
A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is presented in this paper. Circuits exhibit temperature variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the… CONTINUE READING