Temperature Effect on Delay for Low Voltage Applications

@inproceedings{Daga1998TemperatureEO,
  title={Temperature Effect on Delay for Low Voltage Applications},
  author={Jean Michel Daga and E. Ottaviano and Daniel Auvergne},
  booktitle={DATE},
  year={1998}
}
This paper presents one of the first analysis of the temperature dependence of CMOS integrated circuit delay at low voltage. Based on a low voltage extended Sakurai's a-power current law, a detail analysis of the temperature and voltage sensitivity of CMOS structure delay is given. Coupling effects between temperature and voltage are clearly demonstrated. Specific derating factors are defined for the low voltage range (1-3VT0). Experimental validations are obtained on specific ring oscillators… CONTINUE READING
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