Technology scaling on High-K & Metal-Gate FinFET BTI reliability

@article{Lee2013TechnologySO,
  title={Technology scaling on High-K & Metal-Gate FinFET BTI reliability},
  author={Kyong Taek Lee and Wonchang Kang and E. S. Chung and Gunrae Kim and Hyewon Shim and Hyunwoo Lee and Hyejin Kim and Minhyeok Choe and Nae-in Lee and Anuj Patel and Junekyun Park and Jongwoo Park},
  journal={2013 IEEE International Reliability Physics Symposium (IRPS)},
  year={2013},
  pages={2D.1.1-2D.1.4}
}
High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on… CONTINUE READING
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