Technology mapping for low power in logic synthesis

@article{Tiwari1996TechnologyMF,
  title={Technology mapping for low power in logic synthesis},
  author={Vivek Tiwari and Pranav Ashar and Sharad Malik},
  journal={Integration},
  year={1996},
  volume={20},
  pages={243-268}
}
Traditionally, three metrics have been used to evaluate the quality of logic circuits { size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another… CONTINUE READING
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