Technology independent yield-aware place & route strategy for printed electronics gate array circuits

Abstract

We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.

Cite this paper

@article{Llamas2016TechnologyIY, title={Technology independent yield-aware place & route strategy for printed electronics gate array circuits}, author={Mart{\'i}n Llamas and Jordi Carrabina and Llu{\'i}s Ter{\'e}s}, journal={2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)}, year={2016}, pages={1-1} }