Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

@article{Chen2015TechnologydesignCO,
  title={Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip},
  author={Pai-Yu Chen and Deepak Kadetotad and Zihan Xu and Abinash Mohanty and Binbin Lin and Jieping Ye and Sarma B. K. Vrudhula and Jae-sun Seo and Yu Cao and Shimeng Yu},
  journal={2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
  year={2015},
  pages={854-859}
}
Technology-design co-optimization methodologies of the resistive cross-point array are proposed for implementing the machine learning algorithms on a chip. A novel read and write scheme is designed to accelerate the training process, which realizes fully parallel operations of the weighted sum and the weight update. Furthermore, technology and design parameters of the resistive cross-point array are co-optimized to enhance the learning accuracy, latency and energy consumption, etc. In contrast… CONTINUE READING
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