Technologies to further reduce soft error susceptibility in SOI

@article{Oldiges2009TechnologiesTF,
  title={Technologies to further reduce soft error susceptibility in SOI},
  author={Phil Oldiges and Robert H. Dennard and David F. Heidel and Tak H. Ning and Kenneth P. Rodbell and Henry H. K. Tang and Michael S. Gordon and Larry Wissel},
  journal={2009 IEEE International Electron Devices Meeting (IEDM)},
  year={2009},
  pages={1-4}
}
Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements. Our methodology is first introduced, and the following techniques are examined in detail: 1) Body thinning, 2) carrier lifetime reduction, 3) body contacts, 4) stacked devices, and 5) parallel devices. Finally, the advantages and disadvantages of all methods are described. 
Highly Cited
This paper has 35 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 12 extracted citations

Soft Error Resiliency Characterization on IBM BlueGene/Q Processor

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) • 2014
View 6 Excerpts
Highly Influenced

Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd

IEEE Transactions on Nuclear Science • 2017
View 2 Excerpts

System-Level Effects of Soft Errors in Uncore Components

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2017
View 1 Excerpt

Understanding soft errors in uncore components

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) • 2015
View 2 Excerpts

Utilizing device stacking for area efficient hardened SOI flip-flop designs

2014 IEEE International Reliability Physics Symposium • 2014

References

Publications referenced by this paper.

52

H. Tang, IBM JRD
p. 233 • 2008
View 2 Excerpts

Similar Papers

Loading similar papers…