Techniques for foundry identification

@article{Wendt2014TechniquesFF,
  title={Techniques for foundry identification},
  author={James Bradley Wendt and Farinaz Koushanfar and Miodrag Potkonjak},
  journal={2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2014},
  pages={1-6}
}
Foundry identification is essential for many tasks including intellectual property protection, trust, and preventing counterfeiting. In this paper, we introduce statistical techniques for foundry detection, specifically for identifying from which foundry a particular chip originates from. The key idea is to consider the distributions of channel lengths and threshold voltages after employing a variant of SAT that extracts these two metrics. We apply Kolmogorov-Smirnov and other statistical tests… 
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References

SHOWING 1-10 OF 27 REFERENCES

Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach

A methodology for unique identification of integrated circuits (ICs) that addresses untrusted fabrication and other security problems, and introduces a number of novel security and authentication protocols, such as hardware metering, challenge-based authentication and prevention of software piracy.

Hardware Trojan horse detection using gate-level characterization

A technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay is introduced, which utilizes linear programming to solve a system of equations created using nondestructive measurements of power or delays to detect embedded HTHs.

Scalable Hardware Trojan Diagnosis

  • Sheng WeiM. Potkonjak
  • Computer Science, Physics
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2012
This work has developed a scalable HT detection and diagnosis approach that uses segmentation and gate level characterization (GLC) and is capable of detecting and diagnosing HTs accurately on large circuits.

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

It is demonstrated that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

Robust passive hardware metering

By using threshold voltage for ID creation, this work is able to quantify the probability of coincidence between legitimate and pirated ICs, thus for the first time quantitatively and accurately demonstrating the effectiveness of a hardware metering approach.

Gate-level characterization: Foundations and hardware security applications

The simulation results show that the thermally conditioned GLC approach is capable of characterizing all the gates with an average error less than the measurement error, and it can detect HTHs with 100% accuracy on a target circuit.

Analysis and Modeling of CD Variation for Statistical Static Timing

This study studies 5 different correlation models and their associated SSTA methods using 35420 critical dimension measurements that were extracted from 23 reticles on 5 wafers in a 130nm CMOS process and shows that the simple models provide comparable accuracy to that of the more complex ones, while incurring significantly less runtime and implementation difficulty.

Hardware-Based Public-Key Cryptography with Public Physically Unclonable Functions

Using PPUFs, this work has developed conceptually new secret key exchange and public key protocols that are resilient against physical and side channel attacks and do not employ unproven mathematical conjectures.

Hardware metering

  • F. KoushanfarGang Qu
  • Computer Science
    Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
  • 2001
This work introduces the first hardware metering scheme that enables reliable low overhead proofs for the number of manufactured parts and establishes the connection between the requirements for hardware and synthesis process.

The bidirectional polyomino partitioned PPUF as a hardware security primitive

Next generation CMOS-compatible technologies, such as memristors and nanowires, whose components exhibit non-linear circuit characteristics, are proposed to use for the creation of public physical unclonable functions, and a novel architecture of PPUF polyomino partitioning is introduced.