Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs

@article{Oza2014TechniquesFS,
  title={Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs},
  author={Amrita Oza and Poonam Kadam},
  journal={International Journal of Computer Applications},
  year={2014},
  volume={97},
  pages={10-13}
}
  • Amrita Oza, Poonam Kadam
  • Published 18 July 2014
  • Engineering, Computer Science
  • International Journal of Computer Applications
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The… 
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References

SHOWING 1-10 OF 13 REFERENCES
Analysis of sub threshold leakage reduction techniques in deep sub micron regime for CMOS VLSI circuits
  • R. Anjana, Ajay Kumar Somkuwar
  • Engineering
    2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)
  • 2013
Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap…
Minimization of Leakage Current in VLSI Design
To meet the ever-increasing demand of high performance systems, more and more functions are integrated into single chip by scaling down the size of device. Leakage current is becoming an increasingly…
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
TLDR
The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits.
LCPMOS : An Area Efficient Leakage Power Reduction In CMOS Circuits
Article history: Received Accepted Available online 18 Oct. 2014 03 Nov. 2014 05 Nov. 2014 In deep submicron technologies, leakage power becomes a key for a low power design due to its ever…
Reduction of Power Dissipation in Logic Circuits
TLDR
A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic, in which both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors.
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Optimal Body Biasing for Minimum Leakage Power in Standby Mode
TLDR
A new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively is described.
Leakage control with efficient use of transistor stacks in single threshold CMOS
TLDR
The proposed technique identifies a low-leakage state and insert leakage-control transistors only where needed and supports a standard-cell-design flow, and minimizes performance impact.
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
TLDR
Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
somukwar “Analysis of Sub threshold Leakage Reduction Techniques in Deep Sub Micron Regime for CMOS VLSI Circuits,
  • Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT),
  • 2013
...
...