Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs

@article{Oza2014TechniquesFS,
  title={Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs},
  author={Amrita Oza and Poonam Kadam},
  journal={International Journal of Computer Applications},
  year={2014},
  volume={97},
  pages={10-13}
}
  • Amrita Oza, Poonam Kadam
  • Published 18 July 2014
  • Engineering, Computer Science
  • International Journal of Computer Applications
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The… 
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