Tagless Two-level Branch Prediction Schemes


Per-address two-level branch predictors have been shown to be among the best predictors and have been implemented in current microprocessors. However, as the cycle time of modern microprocessors continue to decrease, the implementation of set-associative per-address twolevel branch predictors will become more difficult. In this paper, we revisit and analyze an alternative tagless, direct-mapped approach which is simpler, requires lower power, and has faster access time. The tagless predictor can also offer comparable performance to current setassociative designs since removal of tags allows more resources to be allocated for the predictor and branch target buffer (BTB). Further, removal of tags allows decoupling of the per-address predictors from the BTB, allowing the two components to be optimized individually. We show that tagless predictors are better than tagged predictors because of opportunities for better misshandling. Finally, we examine the system cost-benefit for tagless per-address predictors across a wide design space using equal-cost contours. We also study the sensitivity of performance to the workloads by comparing results from the Instruction Benchmark Suite (IBS) and SPEC CINT95. Our work provides principles and quantitative parameters for optimal configurations of such predictors. Tag-less Two-level Branch Prediction Schemes 2

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@inproceedings{Chen1996TaglessTB, title={Tagless Two-level Branch Prediction Schemes}, author={I-Cheng K. Chen and Chih-Chieh Lee and Matthew A. Postiff and Trevor N. Mudge}, year={1996} }