TTHLS: an HLS tool for testable hardware generation

@article{Ravi2017TTHLSAH,
  title={TTHLS: an HLS tool for testable hardware generation},
  author={S. Ravi and M. Joseph},
  journal={Design Autom. for Emb. Sys.},
  year={2017},
  volume={21},
  pages={231-246}
}
This paper presents a new methodology to incorporate testability to Technology driven high-level synthesis, which is a customized high level synthesis approach based on the target technology. This new methodology called testable technology driven high-level synthesis, generates testable hardware from the corresponding HDL input. Testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area and power consumption than the conventional… CONTINUE READING