TSV reveal etch for 3D integration

@article{Olson2011TSVRE,
  title={TSV reveal etch for 3D integration},
  author={Stephen Olson and Klaus Hummler},
  journal={2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International},
  year={2011},
  pages={1-4}
}
In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etch. We show the results of TSV reveal using both a wet and dry etch. A set of measurements is performed on the TSV wafers and the bonded stack to select etch parameters to achieve the desired TSV reveal height after the etch. We show that even extremely tight process control of… CONTINUE READING
Highly Cited
This paper has 20 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 16 extracted citations

Front-side mid-level Tungsten TSV integration for high-density 3D applications

2016 IEEE International 3D Systems Integration Conference (3DIC) • 2016
View 4 Excerpts
Highly Influenced

TSV reveal height and dimension metrology by the TSOM method

Victor Vartaniana, Ravikiran Attotab, Haesung Parkb, George Orjib, Richard A. Allena
2014
View 6 Excerpts
Highly Influenced

Thermal-mechanical reliability analysis of connection structure between redistribution layer and TSV for MEMS packaging

2016 IEEE 11th Annual International Conference on Nano/Micro Engineered and Molecular Systems (NEMS) • 2016

An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow

2015 IEEE 65th Electronic Components and Technology Conference (ECTC) • 2015
View 2 Excerpts

Enabling wet etch process for TSV reveal high-volume manufacturing

2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) • 2015

Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal

2014 International 3D Systems Integration Conference (3DIC) • 2014
View 1 Excerpt

Wet silicon etch process for TSV reveal

2014 IEEE 64th Electronic Components and Technology Conference (ECTC) • 2014
View 2 Excerpts

References

Publications referenced by this paper.
Showing 1-4 of 4 references

Advanced wafer thinning and handling for through silicon via technology

2011 IEEE 61st Electronic Components and Technology Conference (ECTC) • 2011
View 1 Excerpt

Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's

2011 IEEE 61st Electronic Components and Technology Conference (ECTC) • 2011
View 1 Excerpt

Novel thinning/backside passivation for substrate coupling depression of 3D IC

2011 IEEE 61st Electronic Components and Technology Conference (ECTC) • 2011
View 1 Excerpt

Similar Papers

Loading similar papers…