Corpus ID: 212441645

TSMC-CMOS TECHNOLOGY BASED HIGH SPEED LOW POWER PULSE TRIGGERED FLIP FLOP

@inproceedings{Keerthana2016TSMCCMOSTB,
  title={TSMC-CMOS TECHNOLOGY BASED HIGH SPEED LOW POWER PULSE TRIGGERED FLIP FLOP},
  author={P C Sai Keerthana and M M Gyathri},
  year={2016}
}
  • P C Sai Keerthana, M M Gyathri
  • Published 2016
  • Practically, clocking system like flip-flop (FF) consumes large portion of total chip power as high as 50%. In this brief, a novel low-power pulse-triggered flip-flop (P-FF) design is presented. Here an explicit type pulsetriggered structure and a modified true single phase clock latch based on a signal feed-through scheme is used. Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional transmission gate (TG) and master-slave based FFs in high-speed… CONTINUE READING

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