Corpus ID: 212441645

TSMC-CMOS TECHNOLOGY BASED HIGH SPEED LOW POWER PULSE TRIGGERED FLIP FLOP

@inproceedings{Keerthana2016TSMCCMOSTB,
  title={TSMC-CMOS TECHNOLOGY BASED HIGH SPEED LOW POWER PULSE TRIGGERED FLIP FLOP},
  author={P. Keerthana and M M Gyathri},
  year={2016}
}
Practically, clocking system like flip-flop (FF) consumes large portion of total chip power as high as 50%. In this brief, a novel low-power pulse-triggered flip-flop (P-FF) design is presented. Here an explicit type pulsetriggered structure and a modified true single phase clock latch based on a signal feed-through scheme is used. Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional transmission gate (TG) and master-slave based FFs in high-speed… Expand

Figures from this paper

References

SHOWING 1-10 OF 26 REFERENCES
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
  • Y. Hwang, Jin-Fa Lin, M. Sheu
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2012
TLDR
A novel low-power pulse-triggered flip-flop design is presented that features the best power-delay-product performance in seven FF designs under comparison and a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. Expand
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS
TLDR
This work designs and test a D-flip-flop, known as adaptive-coupling flip- flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-Flop (TGFF). Expand
Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors
Flip-flops and latches are crucial elements of a design from both a delay and energy standpoint. We compare several styles of single edge-triggered flip-flops, including semidynamic and static withExpand
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
TLDR
Applying clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000times in the idle mode with negligible power and delay overhead in the active mode. Expand
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration
TLDR
A new static dual edge-triggered flip-flop that incorporates no precharging and conditional discharging to reduce the switching activity at the internal node efficiently and hence, the power dissipation is very much reduced. Expand
Conditional-capture flip-flop for statistical power reduction
TLDR
The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power Savings of around 67%, as compared to conventional flip- flops. Expand
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF canExpand
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design
TLDR
Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain, and that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷40 % energy savings and at a very small speed performance penalty. Expand
Conditional pre-charge techniques for power-efficient dual-edge clocking
TLDR
A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented, particularly suitable for low-power applications. Expand
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit
TLDR
A comparison of the most representative flip-flop classes and topologies in a 65-nm CMOS technology is carried out to derive several considerations on each FF class and to identify the best topologies for a targeted application. Expand
...
1
2
3
...