Corpus ID: 212525765

TRANSPOSED FORM OF FOLDED FIR FILTER

@inproceedings{Subramanian2017TRANSPOSEDFO,
  title={TRANSPOSED FORM OF FOLDED FIR FILTER},
  author={K. Subramanian and D. Prema and S. Muthukrishnan},
  year={2017}
}
The designing method of folded finite-impulse response (FIR) filter on pipelined array based multiplier arrays is presented in this paper. The design is considered at the bit-level of the pipelined multiplier array and internal delays are fully exploited in order to reduce power consumption and hardware complexity, transposed FIR filter forms is considered. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter… CONTINUE READING

Figures from this paper

References

SHOWING 1-10 OF 20 REFERENCES
Reconfigurable Filter Coprocessor Architecture for DSP Applications
  • 9
A Suggestion for a Fast Multiplier
  • 1,242
A Two's Complement Parallel Array Multiplication Algorithm
  • 659
Calculation of minimum number of registers in arbitrary life time chart
  • K. Parhi
  • Computer Science
  • Proceedings of 7th International Conference on VLSI Design
  • 1994
  • 22
Self-powered Low Power Signal Processing
  • 29
  • PDF
Asynchronous design methodologies: an overview
  • 626
  • PDF
Image and video coding-emerging standards and beyond
  • 85
  • PDF