• Corpus ID: 212525765


  author={Kumbakonam Govindarajan Subramanian and Dr. R. Prema and S. Muthukrishnan},
The designing method of folded finite-impulse response (FIR) filter on pipelined array based multiplier arrays is presented in this paper. The design is considered at the bit-level of the pipelined multiplier array and internal delays are fully exploited in order to reduce power consumption and hardware complexity, transposed FIR filter forms is considered. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter… 

Figures from this paper


Synthesis of control circuits in folded pipelined DSP architectures
The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators using the technique used to derive the control circuitry of the hardware architecture.
Reconfigurable Filter Coprocessor Architecture for DSP Applications
This paper presents a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications that can be reconfigured to support a wide variety of filtering computations.
Low-power signal processing system design for wireless applications
The design principles applicable to wireless signal processing systems are described, using a portable video-on-demand system as an example, for implementing a low-power video compression/decompression system at power levels that are two orders of magnitude below existing solutions.
A Suggestion for a Fast Multiplier
  • C. Wallace
  • Computer Science
    IEEE Trans. Electron. Comput.
  • 1964
A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
A Two's Complement Parallel Array Multiplication Algorithm
An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described, which is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit.
Calculation of minimum number of registers in arbitrary life time chart
  • K. Parhi
  • Computer Science
    Proceedings of 7th International Conference on VLSI Design
  • 1994
This paper presents a general approach to calculate the minimum number of registers in any digital signal processing (DSP) circuit for any arbitrarily specified life-time chart and periodicity of
DSP design tool requirements for embedded systems: A telecommunications industrial perspective
The trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR)1 and the tools needed to address them are described and a proposal for a next generation DSP design environment for telecommunication applications is presented.
Self-powered Low Power Signal Processing
A chip has been designed and tested t o demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. Calculations show that power on the order of
Asynchronous design methodologies: an overview
This work examines the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies, which include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and complication-based quasi-delay-insensitivity circuits.
Image and video coding-emerging standards and beyond
This work discusses coding standards for still images and motion video, and describes some directions beyond the standards such as hybrid coding of graphics/photo images, MPEG-7 for multimedia metadata, and possible new technologies.