TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model

  title={TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model},
  author={Akihiro Takamura and Masashi Kuwako and Masashi Imai and Taro Fujii and Motokazu Ozawa and Izumi Fukasaku and Yoichiro Ueno and Takashi Nanya},
Asynchronousdesignhas a potential of solving many difficulties, such as clock skew and power consumption, which synchronouscounterpartsufferswith currentandfuture VLSI technologies. This paperproposesa new delay model,the scalable-delay-insensitive (SDI) model,for dependableandhigh-performanceasynchronousVLSIsystem design.Then,basedon theSDI model,thepaperpresents the design,chip implementation,and evaluationresultsof a 32-bit asynchronousmicroprocessorTITAC-2 whoseinstructionset is basedon the… CONTINUE READING
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