TITAC-2: An Asynchronous 32-bit Microprocessor

  title={TITAC-2: An Asynchronous 32-bit Microprocessor},
  author={Akihiro Takamura and Motokazu Ozawa and Izumi Fukasaku and Taro Fujii and Yoichiro Ueno and Masashi Imai and Masashi Kuwako and Takashi Nanya},
With the wire-delay problem moving into dominance in VLSI chip design, a fundamental limitation is being revealed in performance and dependability of synchronous systems which require global clock distribution with as little skew as possible. The worst-case delay is influenced not only by design and fabrication process but also by the operating environment, e.g. the power supply voltage and temperature. Asynchronous systems, with no global clock, can intrinsically enjoy ; 1) averagecase… CONTINUE READING


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Publications referenced by this paper.
Showing 1-3 of 3 references

TITAC-2 : A 32-bit Scalable-Delay-Insensitive Microprocessor

Takashi Nanya, Akihiro Takamura, +10 authors Masao Fukuma
InHOT CHIPS IX, • 1997

, Hiroki Fujimoto , Osamu Fujita , Masakazu Yamashina , and Masao Fukuma . TITAC - 2 : A 32 - bit Scalable - Delay - Insensitive Microprocessor

Takashi Nanya, Akihiro Takamura, +6 authors Fuyuki Okamoto

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