TFET based Ternary Logic Gates & Arithmetic Circuits

@inproceedings{Deshpande2012TFETBT,
  title={TFET based Ternary Logic Gates & Arithmetic Circuits},
  author={Rashmi B Deshpande and K. Dakhole},
  year={2012}
}
Scaling of conventional CMOS devices has reduced the device dimensions from 10 mm in 1970s to 0.1 μm in a present day. According to ITRS (i.e. International Technology Roadmap for Semiconductors ) we are going to face the brick wall in 2015 if we continue in the same development speed. This will not be possible for us to maintain the pace forecasted by… CONTINUE READING