Systolic and Super-Systolic Multipliers for Finite Field $GF(2^{m})$ Based on Irreducible Trinomials

  title={Systolic and Super-Systolic Multipliers for Finite Field \$GF(2^\{m\})\$ Based on Irreducible Trinomials},
  author={Pramod Kumar Meher},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
Novel systolic and super-systolic architectures are presented for polynomial basis multiplication over GF(2m) based on irreducible trinomials. By suitable cut-set retiming, we have derived here an efficient bit-level-pipelined bit-parallel systolic design for binary field multiplication which requires fewer gates and registers and involves nearly half the time-complexity of the corresponding existing design. We have also suggested a digit-level-pipelined design, which involves lower latency… CONTINUE READING
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FPGA implementation of an efficient multiplier over finite fields GF (2m)

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