Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m)

@article{Meher2007SystolicFF,
  title={Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m)},
  author={Pramod Kumar Meher},
  journal={2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)},
  year={2007},
  pages={134-139}
}
It presents a high-throughput hardware-efficient semi-systolic linear array for a serial-parallel implementation of finite field multiplier over GF(2m) using bidirectional modulo reduction technique. Necessary recurrence relations are formulated and a pair of dependence graphs (DG) are designed for least significant bit (LSB) and most significant bit (MSB) elimination algorithms for modular reduction. Both the DGs are merged together and mapped into a fully-pipelined linear array architecture… CONTINUE READING
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