# Systolic-Arrays for Modular Exponentiation Using Montgomery Method (Extended Abstract)

@inproceedings{Iwamura1992SystolicArraysFM, title={Systolic-Arrays for Modular Exponentiation Using Montgomery Method (Extended Abstract)}, author={Keiichi Iwamura and Tsutomu Matsumoto and Hideki Imai}, booktitle={EUROCRYPT}, year={1992} }

This paper proposes two ideas for modular exponentiation using Montgomery method. (1) A novel algorithm for modular exponentiation without operation of subtracting N for every Montgomery's modular multiplication (MMM). (2) Two types of systolic-array for MMM which can realize more efficient and flexible chip implementation than the array in [1].

## 21 Citations

Efficient Fixed-Size Systolic Arrays for the Modular Multiplication

- Computer Science, MathematicsCOCOON
- 1999

This paper presents an efficient fixed-size systolic array for Montgomery's modular multiplication designed by the LPGS (Locally Parallel Globally Sequential) partition method and addresses a computation pipelining technique, which improves the throughput and minimizes the buffer size used.

Hardware implementation of a Montgomery modular multiplier in a systolic array

- Computer Science, MathematicsProceedings International Parallel and Distributed Processing Symposium
- 2003

A hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) and RSA cryptosystems is described, and modular exponentiation based on Montgomery's Multiplication Method (MMM) is presented.

A novel systolic VLSI architecture for fast RSA modular multiplication

- Computer ScienceProceedings. IEEE Asia-Pacific Conference on ASIC,
- 2002

This paper proposes a modified version of Montgomery's modular multiplication algorithm using a precomputed addition result, and then the proposed algorithm is mapped onto linear systolic arrays of processing elements for modular multiplication.

Montgomery in Practice: How to Do It More Efficiently in Hardware

- Computer ScienceCT-RSA
- 2002

This work presents modular exponentiation based on Montgomery's method without any modular reduction achieving the best possible bound according to C. Walter.

Montgomery Multiplication Using Vector Instructions

- Computer ScienceSelected Areas in Cryptography
- 2013

A parallel approach to compute interleaved Montgomery multiplication which is particularly suitable to be computed on 2-way single instruction, multiple data platforms as can be found on most modern computer architectures in the form of vector instruction set extensions is presented.

A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs

- Computer ScienceJ. Hardw. Syst. Secur.
- 2017

An efficient hardware implementation of the Coarsely Integrated Operand Scanning (CIOS) method of Montgomery modular multiplication combined with an effective systolic architecture designed with a two-dimensional array of processing elements is discussed.

Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

- Computer Science
- 1995

This Ph.D. thesis treats the calculation of modular exponentials using verylarge operands using very large operands through a top-down approach: modular multiplication, modular addition, addition, modular reduction, and quotient determination.

Systolic array based on fast modular multiplication algorithm for RSA cryptosystem

- Computer ScienceProceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030)
- 1999

A new modular multiplication algorithm is first proposed for increasing the computation speed of addition operations and then a bit-level systolic array architecture is designed for the RSA public…

A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs

- Computer ScienceSPACE
- 2016

An efficient hardware implementation of the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery modular multiplication combined with an effective systolic architecture designed with a Two-dimensional array of Processing Elements is discussed.

A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems

- Computer ScienceIACR Cryptol. ePrint Arch.
- 2016

An efficient hardware implementation of the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery modular multiplication combined with an effective systolic architecture designed with a Two-dimensional array of Processing Elements is discussed.

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