Systematic design and modelling of high-resolution , high-speed pipeline ADCs

  title={Systematic design and modelling of high-resolution , high-speed pipeline ADCs},
  author={Matteo Parenti and Davide Vecchi and Andrea Boni and Giovanni Chiorboli},
This paper describes a suitable mathematical model for the design of high-speed, high-resolution pipeline ADCs. The effect of capacitor mismatch and finite amplifier bandwidth and gain on the converter INL and DNL are accurately modelled. On the basis of this model a design optimisation method is provided. 2005 Elsevier Ltd. All rights reserved. 


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Publications referenced by this paper.
Showing 1-8 of 8 references

A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) • 2004
View 1 Excerpt

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

IEEE Journal of Solid-State Circuits • 2004
View 1 Excerpt

A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) • 2001
View 1 Excerpt

Systematic design for optimization of high - speed selfcalibrated pipelined A / D converters , IEEETrans

J. C. Vital J. Goes, J. E. Franca
Solid - State Circ . • 2001

Systematic design for optimization of high-speed self-calibrated pipelined A/D converters, IEEETrans.Circ.Syst

J. Goes, J. C. Vital, J. E. Franca
View 1 Excerpt

Bacrania, A 15-b 1- Msample/s digitally self-calibrated pipeline ADC

A. N. Karanicolas, K.L.H.S. Lee
IEEE J. Solid-State Circ • 1993
View 1 Excerpt

A 13-b 2.5-MHz selfcalibrated pipelined A/D converter in 3-lm CMOS

Y. M. Lin, B. Kim, P. R. Gray
IEEE J. Solid-State Circ • 1991
View 1 Excerpt

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