Systematic IEEE rounding method for high-speed floating-point multipliers


For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence… (More)


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@article{Quach2004SystematicIR, title={Systematic IEEE rounding method for high-speed floating-point multipliers}, author={Nhon T. Quach and Naofumi Takagi and Michael J. Flynn}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, year={2004}, volume={12}, pages={511-521} }