System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes

  title={System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes},
  author={A. Chandra and K. Chakrabarty},
  journal={IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.},
  • A. Chandra, K. Chakrabarty
  • Published 2001
  • Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • We present a new test-data compression method and decompression architecture based on variable-to-variable-length Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SoC). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. In addition, the novel interleaving decompression architecture allows… CONTINUE READING
    363 Citations
    Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding
    • A. Chandra, K. Chakrabarty
    • Computer Science
    • Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
    • 2001
    • 36
    • PDF
    Test data compression and decompression based on internal scanchains and Golomb coding
    • 46
    • PDF
    A Multi-Code Compression Technique for Reducing System-On-Chip Test Time
    Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression
    • 67
    • Highly Influenced
    A new test data compression method for system-on-a-chip
    • B. Ye, M. Luo
    • Computer Science
    • 2010 3rd International Conference on Computer Science and Information Technology
    • 2010
    • 2
    • PDF
    Nine-coded compression technique for testing embedded cores in SoCs
    • 147
    • PDF
    How effective are compression codes for reducing test data volume?
    • 33
    • PDF
    Test data compression based on Variable Prefix Dual-Run-Length Code
    • Y. Yu, Zhiming Yang, Xiyuan Peng
    • Computer Science
    • 2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings
    • 2012
    • 10
    • Highly Influenced
    Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression
    • 45
    • PDF


    Scan vector compression/decompression using statistical coding
    • 269
    • PDF
    Test vector decompression via cyclical scan chains and its application to testing core-based designs
    • A. Jas, Nur A. Touba
    • Computer Science
    • Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)
    • 1998
    • 298
    • PDF
    Design of built-in test generator circuits using width compression
    • 35
    Built-in test pattern generation for high-performance circuits using twisted-ring counters
    • 58
    An efficient method for compressing test data
    • 52
    Built-in self testing of sequential circuits using precomputed test sets
    • 73
    COMPACT: a hybrid method for compressing test data
    • 63
    • PDF
    Deterministic Built-in Pattern Generation for Sequential Circuits
    • 48
    • PDF
    Test requirements for embedded core-based systems and IEEE P1500
    • Y. Zorian
    • Engineering, Computer Science
    • Proceedings International Test Conference 1997
    • 1997
    • 150
    Efficient BIST TPG design and test set compaction via input reduction
    • 62
    • PDF