System-level Max POwer (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks

  title={System-level Max POwer (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks},
  author={Karthik Ganesan and Jungho Jo and William Lloyd Bircher and Dimitris Kaseridis and Zhibin Yu and Lizy Kurian John},
  journal={2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)},
  • K. Ganesan, Jungho Jo, L. John
  • Published 11 September 2010
  • Computer Science
  • 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)
To effectively design a computer system for the worst case power consumption scenario, system architects often use hand-crafted maximum power consuming benchmarks at the assembly language level. These stressmarks, also called power viruses, are very tedious to generate and require significant domain knowledge. In this paper, we propose SYMPO, an automatic SYstem level Max POwer virus generation framework, which maximizes the power consumption of the CPU and the memory system using genetic… 
MAximum Multicore POwer (MAMPO) — An automatic multithreaded synthetic power virus generation framework for multicore systems
  • K. Ganesan, L. John
  • Computer Science
    2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
  • 2011
It is shown that the the power viruses generated by MAMPO consume 40% to 89% more power than running multiple copies of single-core power viruses like MPrime torture test and the most recent published previous work called SYMPO on 3 different parallel multicore system configurations.
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip
This paper presents a versatile power-virus generation technique for Networks-on-Chip (NoC), which allows the designer to quantify the realistically attainable peak power consumption, in order to efficiently guide the design process.
A New Framework Automatically Generates Full-system Multicore Powermarks, or Synthetic Programs with Desired Power Characteristics on Multicore Server Platforms. the Framework Constructs Full-system Power Models with Error Bounds on the Power Estimates and Guides the Design of Energy-efficient and C
A framework to automatically characterize power consumption at the system level in server hardware and generates powermarks, or synthetic programs with specific power characteristics, in a high-level programming language that is versatile to the hardware platform of interest.
Automatic Generation of Peak-Power Traffic for Networks-on-Chip
This paper presents a high-level systematic methodology for generating the appropriate traffic patterns that trigger the peak power consumption in a network-on-chip (NoC), irrespective of the latter’s structural and functional properties.
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing
MicroGrad's fast, resource efficient and accurate test case generation capability allows it to perform rapid evaluation of complex processors and is able to reach tuning goals 4-5x faster compared to alternate mechanisms.
Test Generation for Detection of Malicious Parametric Variations
Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
This paper presents a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind and shows superior power projection accuracy and hardware measurement based analysis.
GeST: An Automatic Framework For Generating CPU Stress-Tests
The generality and effectiveness of the GeST (Generator for Stress-Tests) framework is demonstrated by generating various workloads that stress the CPU power, thermal and voltage margins more than both conventional benchmarks and manually written stress-tests.
DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms
A new framework for the synthesis of DRAM reliability stress viruses, DStress, which automatically searches for the data and memory access patterns that induce the worst-case DRAM error behavior regardless of the internal DRAM design.
Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors
The framework proposed in this paper is the first attempt to automatically generate synthetic benchmark proxies for real world multithreaded applications that characterize the behavior of the workloads in the shared caches, coherence logic, out-of-order cores, interconnection network and DRAM.


Automated microprocessor stressmark generation
This paper demonstrates that with a suitable choice of only 40 hardware-independent program characteristics related to the instruction mix, instruction-level parallelism, control flow behavior, and memory access patterns, it is possible to generate a synthetic benchmark whose performance relates to that of general-purpose and commercial applications.
Wattch: a framework for architectural-level power analysis and optimizations
Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
  • R. Bell, Rajiv Bhatia, Ravel Thai
  • Computer Science
    2006 IEEE International Symposium on Performance Analysis of Systems and Software
  • 2006
This work synthesizes representative PowerPC versions of the SPEC2000, STREAM, TPC-C and Java benchmarks, compile and execute them, and obtains an average IPC within 2.4% of the averageIPC of the original benchmarks and with many similar average workload characteristics.
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
  • K. Ganesan, Jungho Jo, L. John
  • Computer Science
    2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)
  • 2010
This work generates and provides miniature synthetic benchmark clones to solve two pre-silicon design challenges, namely: huge simulation time (weeks to months) when using complete runs of modern workloads like SPEC CPU2006 and the ImplantBench suites based on microarchitecture-independent metrics.
Control techniques to eliminate voltage emergencies in high performance processors
  • R. Joseph, D. Brooks, M. Martonosi
  • Engineering
    The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.
  • 2003
The resonant frequencies most relevant to current microprocessor packages are discussed, a "dI/dt stressmark" is produced that exercises the system at its resonant frequency, and the behavior of more mainstream applications are characterized.
DRAMsim: a memory system simulator
DRAMsim is introduced, a detailed and highly-configurable C-based memory system simulator that implements detailed timing models for a variety of existing memories, including SDRAM, DDR, DDR2, DRDRAM and FB-DIMM, with the capability to easily vary their parameters.
A thermal-aware superscalar microprocessor
  • C. Lim, W. R. Daasch, G. Cai
  • Computer Science, Engineering
    Proceedings International Symposium on Quality Electronic Design
  • 2002
A thermal-aware technique is proposed to minimize the performance impact when thermal/power control mechanism is triggered, which uses on-chip thermal sensors to detect hot-spots within the microprocessor die.
Performance projection of HPC applications using SPEC CFP2006 benchmarks
This paper presents a method for projecting the node level performance of HPC applications using published data of industry standard benchmarks, the SPEC CFP2006, and hardware performance counter data from one base machine.
Thermal Performance Challenges from Silicon to Systems
The demand for high-performance microprocessors has resulted in an escalation of power dissipation as well as heat flux at the silicon level. At the same time, the desire for smaller form-factor
LLVM: a compilation framework for lifelong program analysis & transformation
  • Chris Lattner, V. Adve
  • Computer Science
    International Symposium on Code Generation and Optimization, 2004. CGO 2004.
  • 2004
The design of the LLVM representation and compiler framework is evaluated in three ways: the size and effectiveness of the representation, including the type information it provides; compiler performance for several interprocedural problems; and illustrative examples of the benefits LLVM provides for several challenging compiler problems.