• Corpus ID: 16777804

System Synthesis and Automated Verification : Design Demands for IoT Devices

  title={System Synthesis and Automated Verification : Design Demands for IoT Devices},
  author={Deming Chen and Jason Cong and Swathi Tanjore Gurumani and Wen-mei W. Hwu and Kyle Rupnow and Zhiru Zhang},
The rise of the Internet of Things has led to an explosion of new sensor computing platforms. In a wide variety of application domains, IoT device manufacturers must design and release new IoT devices regularly with shorter product cycles to maintain competitive advantages, differentiate products, sustain growth, and protect market share. However the size and complexity of these systems are also rapidly growing, and the extreme pressures on time-to-market, design cost, and development risk are… 
1 Citations

Figures from this paper

How IOT changes our Life
How IOT affects the authors' daily routine and new advancements of technologies to convert this era through technics for easy life and why it is important to adopt it are discussed.


System-level design solutions: Enabling the IoT explosion
The vision and building blocks of such a design methodolgoy are discussed, which would hopefully become an enabling technology for future IoT development and growth.
High-level Synthesis for Low-power Design
The recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations is discussed and potential opportunities in tackling these challenges are outlined.
Behavioral-level IP integration in high-level synthesis
A general IP integration framework for HLS that supports fixed- and variable-latency IPs without requiring application partitioning is developed and integration of both synthesizable and non-synthesizable IPs is demonstrated.
A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration
This work presents an automated SystemC generation and design space exploration flow alleviating several productivity and design time issues encountered in the current design process and builds analytical models of power and performance that can effectively prune away a large amount of inferior design points very fast and generate Pareto-optimal solution points.
Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis principles
The Hybrid Quick Error Detection (H-QED) approach is presented that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques and incurs less than 2% chip-level area overhead with negligible performance impact.
JIT trace-based verification for high-level synthesis
This paper presents a debug framework that uses just-in-time (JIT) traces and automated insertion of verification code into the generated RTL to assist in debugging an HLS tool and demonstrates that this technique can significantly reduce bug detection latency: often with zero cycle detection.
High-level synthesis with behavioral level multi-cycle path analysis
This paper couple HLS and logic synthesis synergistically so multi-cycle paths can be identified and optimised coherently across both behavioral and logic levels, and proves that the technique examines all reachable circuit state and finds multi- cycle paths including control flow and guarding conditions that improve the flexibility and power of the technique.
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
This work adapts the CUDA programming model into a new FPGA design flow called FCUDA, which efficiently maps the coarse and fine grained parallelism exposed in CUDA onto the reconfigurable fabric, and is the first CUDA-to-FPGA flow to demonstrate the applicability and potential advantage of using the CUda programming model for high-performance computing in FPGAs.
High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors
Multi-core microprocessors integrated with on-die energy-efficient reconfigurable accelerator and co-processor engines to achieve well beyond tera-scale performance in sub-45nm technologies are presented.
High level synthesis of stereo matching: Productivity, performance, and software constraints
This paper examines several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition, and presents an unbiased evaluation of the suitability of using HLS for typical stereo matching software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by autoPilot.