System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

@article{Bobba2014SystemLB,
  title={System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits},
  author={Shashikanth Bobba and Jie Zhang and Pierre-Emmanuel Gaillardon and H.-S. Philip Wong and Subhasish Mitra and Giovanni De Micheli},
  journal={JETC},
  year={2014},
  volume={10},
  pages={33:1-33:19}
}
The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carbon Nanotube (CNT) imperfections. Various layout schemes are studied for enhancing the yield of CNFET standard cell library. With the help of existing ASIC design flow, we perform system-level benchmarking of CNFET circuits and compare them to… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-2 of 2 references

Digital Integrated Circuits, Vol

  • J. M. Rabaey, A. P. Chandrakasan, B. Nikolic.
  • 2, Prentice Hall, Englewood Cliffs, NJ.
  • 2002
Highly Influential
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