Synthesizing power gating sequence in pausible clock based GALS designs

@article{Rajakumari2013SynthesizingPG,
  title={Synthesizing power gating sequence in pausible clock based GALS designs},
  author={A. Rajakumari and N. S. Murthy Sharma and K. Lal Kishore and Vasantha Kumar Petta},
  journal={2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)},
  year={2013},
  pages={65-70}
}
With the improving evolution in VLSI technology most of the digital circuits are becoming SOCs. However most of the SOC systems are synchronous designs and the issues like clock skew, power consumption and EMI are related to clock network. Asynchronous circuits can offer benefits like reduced power and improved performance. However implementing whole design… CONTINUE READING