Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

@article{Kim2015SynthesizableFF,
  title={Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow},
  author={Jin Hee Kim and Jason Helge Anderson},
  journal={2015 25th International Conference on Field Programmable Logic and Applications (FPL)},
  year={2015},
  pages={1-8}
}
We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [1] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream… CONTINUE READING
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