Synthesis of reversible universal QCA gate structure for energy efficient digital design

  title={Synthesis of reversible universal QCA gate structure for energy efficient digital design},
  author={Bibhash Sen and Tanumoy Adak and Anshu S. Anand and Biplab K. Sikdar},
  journal={TENCON 2011 - 2011 IEEE Region 10 Conference},
Quantum-dot Cellular Automata (QCA), a promising alternative to the current CMOS technology, can be a viable solution of thousands of cores in a chip in near future due to its very high device density of 1012device/cm2 and switching speeds of 10ps. On the other hand, the reversible logic is a promising computing paradigm in low power CMOS design, quantum computing, nanotechnology, and optical computing. Again, QCA consume low power which promises the energy efficient design of the logic… CONTINUE READING


Publications referenced by this paper.
Showing 1-10 of 13 references

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2005
View 4 Excerpts
Highly Influenced

dalui and B k sikdar, 'Introducing Universal QCA Logic Gate for Synthesizing Symmetric Functions with Minimum Wire-Crossings, in in Proceedings of ACM ICWET 2010,pp

B.Sen, Manoj Mohapatra, Mamata
View 1 Excerpt

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate

2009 IEEE Computer Society Annual Symposium on VLSI • 2009
View 1 Excerpt

Design and application of universal logic gate based on quantum-dot cellular automata

2008 11th IEEE International Conference on Communication Technology • 2008
View 1 Excerpt

Logic Realization with Coupled QCA Majority-Minority Gate

S. Ditti, P. K. Bhattacharya, P. Mitra, B. K. Sikdar
V DAT, • 2008
View 2 Excerpts

Characterization of universal Nand-Nor­ Inverter QCA gate

B. Sen, B. K. Sikdar
Proceedings of 11th IEEE VLSI Design and Test Symposium, • 2007
View 2 Excerpts

Testing Reversible 1D Arrays for Molecular QCA

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems • 2006
View 2 Excerpts