Synthesis of Concurrent Asynchronous State Machines Using Extended Multi-Burst Graph Specification

Abstract

Extended Huffman machines implemented with basic gates present an optimum latency time and only use the standard-cell technology. Due to the limitations of the existent synthesis methods for asynchronous controllers, these machines are only used for applications where there is limited concurrence between inputs and outputs (I/O concurrence). In these cases, the interaction with the environment happens in the generalized fundamental mode (GFM). This limitation degrades the performance. In this paper we propose an extension of the multi-burst graph specification (MBG) called of extended multi-burst graph (XMBG) that describes asynchronous finite state machines that present a limited amount of I/O concurrence. We also propose a method that synthesizes such controllers as hazard-free extended Huffman machines. Our results show that the XMBG specification was able to describe a few known benchmarks used in interface controller. The experimental results show that there is an area and a latency time improvement for our solution compared to the solutions coming from the Petrify synthesis tool when synthesizing the SoP+latchC architecture. Both solutions require only a standard cell library for their physical implementation. 1 INTRODUCTION The modern digital systems complexity and the necessity of performance improvement has been driven considerable interest in asynchronous design [1]. One promising application area is in Heterogeneous Systems (synchronous and asynchronous mixed modules) [7,8,9]. The behavior of such circuits can be represented as a Signal Transition Graph (STG) [4]. STG is a Petri-net description. Signal transitions describe events. The strength of STG is to describe concurrence between inputs and outputs (I/O concurrence) that occur in heterogeneous systems. However, the larger the number of signals or if there are decisions involving level sensitive signals – (LSS signals) the description becomes very confusing. Furthermore, this type of description may explode in the size [2,3,10]. Petrify [10] is a known synthesis tool that starts from an STG and implements timed controllers using two types of architecture: sum-of-products + latch C (SoP+latchC) or complex gates [10]. The resulting circuits obey the bounded gate and wire delay model and operate according to the generalized fundamental mode (GFM). Complex gates present optimal area and latency time at the expense of a full custom design. SoP+latchC present lower latency time and larger area but require only a standard cell solution [5,6,10]. On the other hand, burst mode specification (BM, XBM) solves the problems related to the STG description but is very limited to describe I/O concurrency [5,6]. It is the natural description of finite state machines. One type of burst mode specification is the multi-burst graph (MBG). It accepts all signals types of the XBM specification and introduces burst operators that allow the description a limited amount of I/O concurrency. There are three types of operators: input burst OR, transition concurrence (CO) and transition sequence (SEQ) [5,6]. We propose an extended version of the MBG (XMBG) that further increases the I/O concurrency allowing the combination of the CO and the SEQ operators. In this work we explain the XMBG specification and show that it may be used to synthesize hazard-free asynchronous controllers as an extended Huffman machine composed exclusively on basic gates [1,7,8]. Such a solution present nice area and latency time properties when compared to the SOP+latchC solution 1 This tool also implements SI controllers. 2 These controllers operate in the I/O mode and they obey the model bounded gate and wire delay. 3 The tools 3D and Minimalist starts this of specification [7,8,9]. from Petrify while keeping the nice properties of a standard cell design methodology. This paper is structured as follows: section 2 presents formally the XMBG specification; section 3 describes concisely the synthesis procedure; section 4 shows our experimental results. Finally section 5 brings the conclusions and future works. 2XMBG SPECIFICATION The burst-mode specification (BM) belongs to the class of specifications that allow multiple-input change. It is represented by a graph in which nodes represent stable states while arcs represent state transitions [9]. Yun [7,8] proposed the extended burst-mode specification (XBM) adding two features: directed don’t care signals (which allow an input signal to change concurrently with an output signal) and level sensitive signals (LSS) with non-monotonic behavior, that may be used with conditionals signals. In order to describe a limited concurrent behavior between input signals and output signals, Oliveira [5], created a new specification called Multi-Burst Graph specification, MBG as an expansion of the XBM specification. Like in the XBM, a MBG represents a state graph in which each node represents a state and each arc represents a transition. Each transition in the MBG can be activated by: 1) an input burst; or 2) a burst expression. We introduce the input burst OR, the transition concurrence (CO) and the transition sequence (SEQ) operators. The use of burst expressions based on these operators increase the possibility to describe I/O concurrence. 2.1I/O Concurrence behavior using burst operators Situation 1: Consider the timing diagram shown in figure 2a. y ad+ / xya+ b+ / x+ CO b+ c+ / y+ a b x c d 2 c+ / y+ a+ b+ / x+

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Cite this paper

@inproceedings{Oliveira2006SynthesisOC, title={Synthesis of Concurrent Asynchronous State Machines Using Extended Multi-Burst Graph Specification}, author={Duarte Lopes de Oliveira and Marius Strum and F{\'a}bio Pereira Alves and J{\'e}fferson Perez R. Costa and Wang Jiang Chau}, year={2006} }