Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier
@article{Mishra2012SynthesisCO,
title={Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier},
author={Sudhanshu K. Mishra and Manoranjan Pradhan},
journal={International Journal of Computer Applications},
year={2012},
volume={41},
pages={13-17}
}In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficiency than the multipliers involving Vedic mathematics formulae. General Terms Karatsuba algorithm, Vedic…
6 Citations
Performance Analysis of Karatsuba Multiplication Algorithm for Different Bit Lengths
- Computer Science
- 2015
High speed vedic multiplier for image processing using FPGA
- Computer Science2016 10th International Conference on Intelligent Systems and Control (ISCO)
- 2016
An approach for image filtering using Vedic Mathematic which performs faster multiplication compared to the conventional algorithms namely Booth and Array Multiplication Algorithm thus reducing the time required for filtering of images.
SQUARE OPERATION IMPLEMENTATION ON RECONFIGURABLE HARDWARE LOGIC TO ATTAIN HIGH SPEED, AREA OPTIMIZATION AND LOW POWER CONSUMPTION
- Computer ScienceJOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES
- 2020
The results were compared with 4-bit as well as 8-bit operation using both algorithms for a square operation are it is observed that the speed of operation is improved by 20 % whereas the hardware resources utilized were reduced by 66 %.
Vedic Mathematics for Digital Signal Processing Operations: A Review
- Computer Science
- 2015
Vedic mathematical algorithms can be proved efficient over traditional methods in FIR and IIR filters for providing effective results in de-noising of biomedical Signal.
Generalizations of n-Term Karatsuba Like Formulae in GF ( 2 n ) with NAYK Algorithm
- Computer Science, Mathematics
- 2017
The first step is to develop a formula that is better than Generalizations of The Karatsuba Algorithm, after then develop an exhaustive search algorithm for all possible existing products, which is referred to as the NAYK algorithm.
References
SHOWING 1-10 OF 28 REFERENCES
MAC Implementation using Vedic Multiplication Algorithm
- Computer Science
- 2011
The paper presents the implementation of MAC (multiplieraccumulator) unit using Vedic multiplier, and the proposed design shows improvement of speed over the design presented in [1].
VLSI Implementation of High Speed DSP algorithms using Vedic Mathematics
- Computer Science, Mathematics
- 2010
It has been found that Urdhva Tiryagbhyam Sutra is most efficient Sutra (algorithm), giving minimum delay for multiplication of all types of numbers, which uses Vedic Mathematics algorithms.
Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
- Computer Science, Mathematics21st International Conference on VLSI Design (VLSID 2008)
- 2008
An architecture to implement Karatsuba Multiplier on an FPGA platform is presented and a masking strategy to prevent power based side channel attacks on the multiplier is developed.
Performance comparison of multipliers for power-speed trade-off in VLSI design
- Computer ScienceICN 2010
- 2010
Comparison study of different multipliers is done for low power requirement and high speed by utilizing Ancient Indian Vedic Mathematics algorithm for multiplication.
Speed Comparison of 16x16 Vedic Multipliers
- Computer Science
- 2011
The paper shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra, and the proposed design has speed improvements as compared to multiplier architecture presented in [5].
Design and Implementation of Long-Digit Karatsuba ’ s Multiplication Algorithm Using Tensor Product Formulation ∗
- Computer Science, Mathematics
- 2003
With the iterative tensor product formula of Karatsuba’s algorithm, an iterative (for loop) program to perform multiplication of long-digit numbers can be derived and the 3 single-digit multiplications can be fully parallelized.
Area efficient hardware implementation of elliptic curve cryptography by iteratively applying Karatsuba's method
- Computer ScienceDesign, Automation and Test in Europe
- 2005
A hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba's method iteratively reduces the area, energy and calculation speed, and is convinced that the benefits of the approach outweigh its drawback.
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs
- Computer ScienceIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2010
This paper introduces the common expression sharing and the complexity analysis on odd-term polynomials to achieve a lower gate bound than previous ASIC discussions and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers over GF(2m) .
Generalizations of the Karatsuba Algorithm for Efficient Implementations
- Computer Science, MathematicsIACR Cryptol. ePrint Arch.
- 2006
In this work we generalize the classical Karatsuba Algorithm (KA) for polynomial multiplication to (i) polynomials of arbitrary degree and (ii) recursive use. We determine exact complexity…