Synergistic Processing in Cell's Multicore Architecture

@article{Gschwind2006SynergisticPI,
  title={Synergistic Processing in Cell's Multicore Architecture},
  author={M. Gschwind and H. P. Hofstee and B. Flachs and M. Hopkins and Yukio Watanabe and T. Yamazaki},
  journal={IEEE Micro},
  year={2006},
  volume={26},
  pages={10-24}
}
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. The streamlined architecture provides an efficient multithreaded execution environment for both scalar and SIMD threads and represents a reaffirmation of the RISC principles of combining leading… Expand
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