Software defined radios ( S D R ) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there i s a plethora of silicon alternatives available for implementing the various functions in a S D R , field programmable gate arrays (FPGAs) are a n attractive option for m a n y of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rate wireless system i s synchronization. This paper i s about carrier and timing synchronization in SDRs using FPGA based signal processors. W e describe and examine a QPSK Costas loop for performing coherent demodulation, and report o n the implications of a n FPGA mechanization. Symbol timing recovery i s addressed using a differential matched filter control system. A tutorial style approach i s adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.