Symmetry Reduction for STE Model Checking

  title={Symmetry Reduction for STE Model Checking},
  author={Ashish Darbari},
  journal={2006 Formal Methods in Computer Aided Design},
In spite of the tremendous success of STE model checking one cannot verify circuits with arbitrary large number of state holding elements. In this paper we present a methodology of symmetry reduction for STE model checking, using a novel set of STE inference rules. For symmetric circuit models these rules provide a very effective reduction strategy. When used as tactics, rules help decompose a given STE property to a set containing several classes of equivalent STE properties. A representative… CONTINUE READING
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