Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

@article{Kim2007SymmetricVP,
  title={Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology},
  author={Daeik Kim and Jonghae Kim and J. O. Plouchart and Choongyeun Cho and Robert Trzcinski and M. Teja Kiran Kumar and Christine Norris},
  journal={IEEE Electron Device Letters},
  year={2007},
  volume={28},
  pages={616-618}
}
This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer… CONTINUE READING