Symbolic model checking for sequential circuit verification

@article{Burch1994SymbolicMC,
  title={Symbolic model checking for sequential circuit verification},
  author={Jerry R. Burch and Edmund M. Clarke and David E. Long and Kenneth L. McMillan and David L. Dill},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1994},
  volume={13},
  pages={401-424}
}
The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x states. Our… CONTINUE READING

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