Symbolic functional vector generation for VHDL specifications

  title={Symbolic functional vector generation for VHDL specifications},
  author={Fabrizio Ferrandi and Franco Fummi and Luca Gerli and Donatella Sciuto},
  journal={Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)},
Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral fault model. First, we generate a reduced number of functional test vectors for each… CONTINUE READING
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