Symbolic fault modeling for switched-capacitor circuits

@article{Cheng2013SymbolicFM,
  title={Symbolic fault modeling for switched-capacitor circuits},
  author={Jiandong Cheng and Guoyong Shi and Andy Tai and Frank Lee},
  journal={2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)},
  year={2013},
  pages={1-4}
}
A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided. 

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
SHOWING 1-3 OF 3 CITATIONS

References

Publications referenced by this paper.
SHOWING 1-10 OF 10 REFERENCES

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

  • G. Shi
  • Analog Integrated Circuits and Signal Processing…
  • 2013

A static l inear behavior analog faul t model for switched­ capacitor circuits

  • H. C. Hong
  • IEEE Trans. on Computer-Aided Design of…
  • 2012
2 Excerpts

Rodriguez-Vazquez, Top-Down Design of High-Peljormance Sigma-Delta Modulators

  • F Medeiro, B. Perez-Verdu
  • 1999

Similar Papers

Loading similar papers…