Symbolic Simulation for Functional Verification with ADLIB and SDL
@article{Cory1981SymbolicSF, title={Symbolic Simulation for Functional Verification with ADLIB and SDL}, author={Wendell E. Cory}, journal={18th Design Automation Conference}, year={1981}, pages={82-89} }
The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence of different levels of abstraction and asynchronous timing.
This paper motivates interest in this problem and provides background information on verification, ADLIB, and SDL. It then discusses approaches for dealing with the problems encountered… CONTINUE READING
Figures and Topics from this paper.
Citations
Publications citing this paper.
SHOWING 1-7 OF 7 CITATIONS
Çêååä Ååìàççë Çê Íaeaeìáçaeaeä Îîêáááááìáçae
VIEW 1 EXCERPT
CITES METHODS
Formal Methods for Functional Verification
VIEW 1 EXCERPT
CITES METHODS
Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
VIEW 2 EXCERPTS
CITES BACKGROUND
Formal sequential equivalence checking of digital systems by symbolic simulation
VIEW 2 EXCERPTS
CITES BACKGROUND
Symbolic Simulation - Techniques and Applications
VIEW 1 EXCERPT
CITES BACKGROUND