Symbolic Model-Checking for Real-Time Circuits and Specifications

Abstract

The verification of real-time properties requires model checking techniques for quantitative temporal structures and real-time temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unit-delay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by low-level circuit verification, the implemented prover can be used for verifying general real-time systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach.

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Cite this paper

@inproceedings{Frl1995SymbolicMF, title={Symbolic Model-Checking for Real-Time Circuits and Specifications}, author={J{\"{u}rgen Fr{\"{o}\ssl and Joachim Gerlach and Thomas Kropf}, year={1995} }